The advantages of monolithically integrated circuits and the emergence of very large scale integration (VLSI) techniques, have made possible denser and higher speed random access memory (RAM). Moreover, the demand for high performance computers has placed an ever increasing requirement for higher performance RAM. In response to these demands, the electronic data processing industry continues to strive for higher performance static RAM devices and processes for making such static RAM devices, especially in cache memory applications.
Generally, the industry has employed emitter-coupled logic (ECL) circuits to meet high performance requirements. In particular, for high performance memory applications, ECL RAM using a complementary transistor switch (CTS) memory cell has been employed.
For instance, in an article entitled, "A 1024--Byte ECL Random Access Memory Using a Complementary Transistor Switch (CTS) Cell", by J. A. Dorler, et al, pages 126-134 IBM Journal of Research and Development, Vol. 25, No. 3, May, 1981, the performance advantages of CTS cells in achieving high circuit density and good performance in silicon RAM are described.
Heretofore, CTS Memory devices employing a vertical NPN transistor and a relatively large lateral PNP transistor in silicon technology are known. Recently, III-V compounds such as gallium arsenide (GaAs), with higher electron mobility, higher transconductance, and less delay associated with less charge storage, have been considered important for high performance applications.
Many efforts have been directed at fabricating complementary vertical NPN and vertical PNP transistors on a monolithic semiconductor device. U.S. Pat. No. 3,959,039 issued May 25, 1976 to Bonis, et al, entitled "Method of Manufacturing Vertical Complementary Bipolar Transistors each with Epitaxial Base Zones" describes a method for realizing an epitaxial region which can serve as the base of a vertical transistor as well as the collector of a second complementary vertical transistor in a Darlington arrangement. Related U.S. Pat. No. 4,122,482 teaches and claims the resulting Darlington device structure.
U.S. Pat. No. 4,485,552 issued Dec. 4, 1984 to Magdo, et al, entitled "Complementary Transistor Structure and Method for Manufacture" teaches a method for making both complementary vertical NPN and vertical PNP transistors having matched performance characteristics, in which transistors are completely isolated from one another.